1. Technical Field
The present invention relates to a write-inhibit circuit for use in a semiconductor integrated circuit including a nonvolatile memory, an ink cartridge 10 including the semiconductor integrated circuit, and an ink-jet recording apparatus in which the ink cartridge is mounted.
2. Background Art
Conventionally, in a case in which a power-supply voltage decreases due to some cause when the desired data is written in a nonvolatile memory built into a semiconductor integrated circuit, miswriting may be performed. To prevent the miswriting, a write-inhibit circuit may be provided in the semiconductor integrated circuit.
FIG. 13 is a block diagram showing an example of a write-inhibit circuit built into a semiconductor integrated circuit. In this figure, a write-inhibit circuit 100 includes a resistor array 101, an operational amplifier 102, a bias circuit 103, a logic gate 104, and a reference-voltage supply 105.
The resistor array 101 is formed by a resistor R1 and a resistor R2 which are connected in series. One end of the resistor R1 is connected to a high-potential power supply VDD. One end of the resistor R2 is connected to a low-potential power supply VSS. By connecting the junction of the resistor R1 and the resistor R2 to the gate of a transistor Q2, a voltage that is divided corresponding to a resistance ratio between the resistor R1 and the resistor R2 is applied to the gate of the transistor Q2.
The operational amplifier 102 is formed such that the transistors Q1 and Q2, which are connected in series, are connected in parallel to transistors Q3 and Q4. The gates of the transistors Q1 and Q3 are connected in common, and are connected to the junction of the transistor Q1 and transistor Q2. The junction of the transistor Q3 and the transistor Q4 is connected as an output end to the gate of a transistor Q6 at the subsequent stage. A reference voltage Vref is applied from the reference-voltage supply 105 to the gate of the transistor Q4.
The bias circuit 103 is provided between a low-potential connection end (the junction of the transistors Q2 and Q4) of the operational amplifier 102 and the low potential power supply VSS, and includes the transistor Q5, which is applied a power-supply voltage Vreg having a predetermined potential, and a transistor Q7 connected in common to the back gate of the transistor Q5.
The logic gate 104 is formed by a NOR gate G11. The NOR gate G11 has one input end to which an inverted signal of a writing request signal WR is input. Also, the junction of the transistor Q6 and the transistor Q7 is connected to the other input end of the NOR gate G11, so that the potential of the junction is input, and an inverted signal of a logical addition of the inputs is output.
In the above-described construction, when the voltage value of the high potential power supply VDD is sufficiently higher than the reference voltage Vref of the reference-voltage supply 105, the output of the operational amplifier 102 is at xe2x80x9cLxe2x80x9d, and the transistor Q6 is in off-state. Then, xe2x80x9cLxe2x80x9d is applied to the other input end of the NOR gate G11, so that the data-writing request signal WR is unchanged and output as a write-control signal WRITE.
In addition, in a case in which the voltage value of the high potential power supply VDD decreases for some reason, the voltage applied to the transistor Q2, which is divided by the resistor array 101, is less than the reference voltage Vref, the output of the operational amplifier 102 is at xe2x80x9cHxe2x80x9d, so that the transistor Q6 is in on-state.
At this time, xe2x80x9cHxe2x80x9d is applied to the other input end of the NOR gate G11. Thus, irrespective of whether the data-writing request signal WR is either at xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d, the write-control signal WRITE is at xe2x80x9cLxe2x80x9d. In other words, the power-supply voltage decreases, and miswriting can be prevented because writing by the data-writing request signal WR cannot be performed.
The write-inhibit circuit 100 has a relatively high detection precision since it uses the operational amplifier 102. However, the write-inhibit circuit 100 has the following defects. Specifically, the write-inhibit circuit 100 must include, other than the operational amplifier 102, the resistor array 101, the bias circuit 103, the logic gate 104, and the reference-voltage supply 105. Among these, in particular, the resistor array 101, the logic gate 104, and the reference-voltage supply 105 are large in circuit size. Accordingly, provision of these in the semiconductor integrated circuit causes a drawback in that the chip area increases.
In addition, in order that the write-inhibit circuit 100 may operate, it is required that, by using the bias circuit 103, a current always flow in the operational amplifier 102. This causes a defect in that the operating current increases increasing the power consumption and generated heat increases.
The present invention is made to solve the above defects in the related art, and an object thereof is to reduce a chip area and to provide a write-inhibit circuit in which power consumption is reduced, a semiconductor integrated circuit using the same, an ink cartridge including the semiconductor integrated circuit, and an ink-jet recording apparatus.
A write-inhibit circuit of the present invention is a write-inhibit circuit using a data-writing request signal as an input and using an output write-control signal to inhibit data writing. The write-inhibit circuit includes a current mirror circuit in which a first transistor array that is formed by connecting in series a plurality of transistors including a depletion transistor, used as a reference-current supply between a high potential power supply and a low potential power supply, is connected in parallel to a second transistor array that is formed by connecting a plurality of transistors between the high potential power supply and the low potential power supply, wherein the write-inhibit circuit leads an output in accordance with the result of comparison between a reference current from the reference-current supply and a current in accordance with the input signal, and when the voltage of the high potential power supply decreases, the write-inhibit circuit leads an output in accordance with the reference current from the reference-current supply.
The second transistor array is formed by connecting in series a first transistor which is connected to the high potential power supply and which is switched on in accordance with the data-writing request signal, a second transistor which allows a current equal to that flowing via the first transistor to flow in the first transistor array, and a third transistor which is switched on together with the first transistor and which forms a current path to the low potential power supply; the first transistor array is formed by connecting in series a fourth transistor which is connected to the high potential power supply and which is switched on in accordance with the data-writing request signal, a fifth transistor having a gate electrode connected in common to the gate terminal of the second transistor, and a sixth transistor as the depletion transistor; and the write-control signal is output from the junction of the fifth transistor and the sixth transistor.
A semiconductor integrated circuit of the present invention includes: the above write-inhibit circuit; a memory cell for storing data at a designated address; and an address generating circuit for sequentially generating addresses for designation in the memory cell. The writing of the data in the memory cell is inhibited based on a write-control signal output from the write-inhibit circuit.
The semiconductor integrated circuit further includes a control means for performing control so as to perform transfer to a low power consumption mode having power consumption less than a normal operating mode for performing a normal operation. The semiconductor integrated circuit may be provided in an ink cartridge, and may perform transfer to the low power consumption mode in response to the termination of a printing operation using the ink cartridge. The address may be initialized when the control means performs transfer to the low power consumption mode.
In the low power consumption mode activated by the control means, the operations of internal circuits are terminated, such as a sense amplifier for generating a signal for reading data stored in the storage means, an address decoder for designating an address in the storage means, a buffer used when data read from the storage means is read, and a latch circuit for latching data read from the storage means.
The transfer to the low power consumption mode, and the initialization of the address generated by the address generating means may be performed based on a control signal input to a common external terminal. The common external terminal is, for example, a chip-select terminal.
An ink cartridge of the present invention includes the above semiconductor integrated circuit, and stores at least the remaining amount of ink.
An ink-jet recording apparatus of the present invention has the above ink cartridge, and uses ink supplied from the ink cartridge to print the desired image information.